The present disclosure relates generally to information handling systems, and more particularly to a power system that utilizes processor core performance state control in an information handling system.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option is an information handling system (IHS). An IHS generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes. Because technology and information handling needs and requirements may vary between different applications, IHSs may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in IHSs allow for IHSs to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, IHSs may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
The power requirements of IHSs are steadily increasing. For example, as processors have added cores and other processing features, the sustainable power requirements, dynamic power requirements, and peak power requirements of the power system have increased. Traditionally, processor thermal design power (TDP) has been used for (indefinitely) sustainable power requirement budgeting purposes, and only a small amount of additional power was budgeted for dynamic power requirements and peak power requirements that are above the TDP of the processor. However, as the number of processor cores has increased (from 1, to 2, to 4, to 8, and to 10 and higher), the ability of all cores to simultaneously transition from an idle state to an active state has driven the dynamic power requirements and peak power requirements rapidly relative to the sustainable power requirements. For example, maximum or peak power (“Pmax”, typically sustainable on the order of milliseconds to tens of milliseconds) has grown from 1.3×TDP, to 1.6×TDP, and up to 2.2×TDP, and dynamic power (“Pdyn”, typically sustainable on the order of hundreds of milliseconds to seconds) has grown from 1.0×TDP, to 1.2×TDP, to 1.6×TDP for some processors in the last 5 years. Processor cores and other computing elements can activate on the order of nanoseconds, which is orders of magnitude faster than conventional monitoring and throttling mechanisms can respond.
Worst case theoretical dynamic power requirements and peak power requirements are typically determined to describe all possible processor usage models, including those that are very unlikely or that may only be realized by a small subset of users and applications. For example, worst case theoretical requirements may consider a small subset of the processor instruction set that is only used in specific high performance computing (HPC) workloads, “thermal virus” level code segments that require micro-architectural knowledge to generate, worst case processor operating parameters (e.g., worst case voltage, temperature, process, etc.), 100% processor/system utilization (typical utilization is between 30-70%), and/or a variety of other worst case scenarios known in the art. As these worst case theoretical dynamic power requirements and peak power requirements have grown, the difference between the actual or measured dynamic power requirements and peak power requirements and those worst case theoretical requirements has grown as well.
Furthermore, denser systems are requiring more and more from the power system. Conventional servers today have 2 to 4 processors, with newer designs having 4 to 8 processors and some emerging architectures having dozens of processors. Other computing elements such as memory, graphics controllers, co-processors, network controllers, drives, etc. are also dramatically increasing their dynamic and peak power requirements compared to their “TDP” or sustainable power requirements. These other computing elements may have dynamic and peak power requirements that have substantially different durations and duty cycles than those required by processors.
As the number of processors and other high-power devices in the system grows, it becomes less and less feasible to budget the power system based on theoretical dynamic power requirements and peak power requirements, as those theoretical requirements drive excessive power systems that are costly, inefficient, and difficult (if not impossible) to implement.
Accordingly, it would be desirable to provide an improved power system.